1. Field of the Invention
The present invention relates to digital power amplifiers and digital/analog converters. More specifically, the present invention relates to a digital power amplifier that can be suitably applied, for example, to a power amplifier for amplifying power of a signal in the audio frequency band by switching operation, and also relates to a digital/analog converter for converting a digital signal into an analog signal by switching operation.
2. Description of the Related Art
Signal amplifiers called class-D amplifiers are known as a form of amplifiers for signals in the audio frequency band.
FIG. 6 shows an example of conventional class-D power amplifier. The class-D power amplifier includes a pulse width modulator 2, a power switching circuit 3, and a low-pass filter 6. 9 denotes a speaker, and 9a denotes a capacitor for blocking DC current.
The power switching circuit 3 is implemented by an N-channel power MOSFET 4 and an N-channel power MOSFET 5. The source of the power MOSFET 4 and the drain of the power MOSFET 5 are connected in series with each other, the drain of the power MOSFET 4 is connected to a power supply Vcc, and the source of the power MOSFET 5 is grounded. The low-pass filter 6 is implemented in the form of an L-filter by a choke coil 7 and a capacitor 8.
Furthermore, a node of the series connection between the source of the power MOSFET 4 and the drain of the power MOSFET 5 is connected to an input end of the choke coil 7. A node between an output end of the choke coil 7 and one end of the capacitor 8 is connected to one drive signal input terminal of the speaker 9 via the capacitor 9a, and the other drive signal input terminal of the speaker 9 and the other end of the capacitor 8 are grounded.
A digital signal S1, for example, a PCM-encoded signal in the audio frequency band, is supplied to the input end of the pulse width modulator 2. The pulse width modulator 2 generates a PWM signal S2 that is pulse width modulated according to change in the signal level of the digital signal S1, and also generates a negative PWM signal S3 having an inverse phase with respect to that of the PWM signal S2. The PWM signal S2 output from the pulse width modulator 2 is supplied to the gate of the MOSFET 4, so that switching of the power MOSFET 4 is controlled according to change in the pulse width of the PWM signal S2. The PWM signal S3 is supplied to the gate of the power MOSFET 5, so that switching of the power MOSFET 5 is controlled according to change in the pulse width of the PWM signal S3.
The PWM signal S2 is pulse width modulated so as to have equal on-period and off-period in a reference period (to be described later), i.e., a duty ratio of 50%, when the signal level of the digital signal S1 is at zero level. The ratio of an on-period or an off-period in the reference period will be referred to herein as a PWM ratio. The PWM signal S2 is pulse width modulated so that the on-period increases and the off-period decreases proportionally as the signal level of the digital signal S1 increases in the positive direction from zero level, whereas the on-period decreases and the off-period increases as the signal level of the digital signal S1 increases in the negative direction from zero level.
The PWM signal S3 output from the pulse width modulator 2 is off when the PWM signal S2 is on in accordance with change in the signal level of the digital signal S1, whereas the PWM signal S3 is on when the PWM signal S2 is off. Accordingly, the power MOSFET 5 is controlled according to the PWM signal S3 so that it is off when the power MOSFET 4 is on whereas it is on when the power MOSFET 4 is off.
Thus, when the signal level of the digital signal S1 in the audio frequency band, supplied to the input end of the pulse width modulator 2, is increasing in the positive direction from zero level, in proportion to the increase, the amount of current that flows into the low-pass filter 6 from the power supply Vcc increases whereas the amount of current that flows out from the low-pass filter 6 to the ground decreases.
Conversely, when the signal level of the digital signal S1 supplied to the input end of the pulse width modulator 2 is decreasing from positive level toward zero level, in proportion to the decrease, the amount of current that flows into the low-pass filter 6 from the power supply Vcc decreases whereas the amount of current that flows out from the low-pass filter 6 to the ground increases. When the signal level of the digital signal S1 reaches zero level, the amount of current that flows into the low-pass filter 6 from the power supply Vcc and the amount of current that flows out from the low-pass filter 6 to the ground become equal, whereby output of the low-pass filter 6 also reaches zero level.
When the signal level of the digital signal S1 in the audio frequency band, supplied to the input end of the pulse width modulator 2, is increasing in the negative direction from zero level, in proportion to the increase, the amount of current that flows into the low-pass filter 6 from the power supply Vcc decreases whereas the amount of current that flows out from the low-pass filter 6 to the ground increases.
Conversely, when the signal level of the digital signal S1 supplied to the input end of the pulse width modulator 2 is decreasing from negative level toward zero level, in proportion to the decrease, the amount of current that flows into the low-pass filter 6 from the power supply Vcc increases whereas the amount of current that flows out from the low-pass filter 6 to the ground decreases. When the signal level of the digital signal S1 reaches zero level, the amount of current that flows into the low-pass filter 6 from the power supply Vcc and the amount of current that flows out from the low-pass filter 6 to the ground become equal, whereby output of the low-pass filter 6 also reaches zero level.
Thus, the conventional class-D power amplifier, having been described with reference to FIG. 6, efficiently amplifies power of a signal input thereto. However, the switching elements that constitute the main part of the class-D amplifier are not ideal; more specifically, switching elements that are available at the current technological level inevitably have on-resistance. Thus, even when the signal level of the digital signal S1 is at zero level, loss due to on-resistance associated with switching of the power MOSFET 4 is unavoidable.
In particular, if the digital signal S1 is an audio signal, the frequency of zero level crossing is high, raising a need for minimizing loss due to on-resistance of switching elements at zero level points.
The present invention has been made in view of the above, and it is an object of the present invention to provide a class-D power amplifier in which effect of switching loss at zero level points is appropriately alleviated.
To this end, the present invention, in one aspect thereof, provides a digital power amplifier including a pulse width modulator for converting an input signal into a pulse width modulated signal according to a signal level of the input signal; an output stage, switching thereof being controlled according to the pulse width modulated signal generated by the pulse width modulator; a detector for detecting the signal level of the input signal; and a control unit for disabling switching operation of the output stage when the detector detects that the signal level of the input signal is zero.
Accordingly, when the signal level of the input signal is at zero level or crossing zero level, switching operation of the output stage is disabled, so that waste of power in the output stage is reduced.
The present invention, in another aspect thereof, provides a digital/analog converter including a pulse width modulator for converting a digital input signal into a pulse width modulated-signal according to a signal level of the digital input signal; an output stage, switching thereof being controlled according to the pulse width modulated signal generated by the pulse width modulator; a detector for detecting the signal level of the digital input signal; and a control unit for disabling switching operation of the output stage when the detector detects that the signal level of the digital input signal is zero.
Accordingly, when the signal level of the digital input signal is at zero level or crossing zero level, switching operation of the output stage is disabled, so that waste of power in the output stage is reduced.